A semiconductor device typically includes a network of circuits that are formed over a substrate. The device may consist of several layers of circuit wiring, with various interconnects being used to connect these layers to each other and any underlying transistors. Generally, as a part of the manufacturing process, vias or contact holes are formed, which are transferred to another layer and then filled with a metal to form interconnects, so that the various layers of circuitry are in electrical communication with each other. Prior art methods of forming interconnects generally rely on a series of lithographic and etching steps to define the positions and dimensions of the vias, which in turn define the positions and dimensions of the corresponding interconnects. To this end, photoresists and hard masks may be employed. However, the dimensions of features formed using conventional optical lithography techniques for volume manufacturing (e.g., 193 nm dry and immersion lithography) have reached the resolution limit of the lithographic tools.
The creation of vias with smaller critical dimensions (CDs), tighter pitches, and better CD uniformity is one of major challenges for future technology nodes; however, printing such via patterns beyond the 22 nm node is expected to be difficult using conventional optical lithography, even with expensive and complicated double patterning processes, resolution enhancement technology (computational lithography) and severe layout design restrictions. Unfortunately, no alternative non-optical lithographic technique with higher resolution capabilities, such as e-beam lithography or extreme ultraviolet lithography (EUV), appears to be ready for high volume manufacturing in the near future. While e-beam direct write lithography is capable of very high resolution, it is a direct-write technique and cannot achieve the necessary wafer throughput levels to make it viable for volume manufacturing. EUV lithography tools have been under development for many years; however, many challenges associated with the source, collection optics, masks, and resists still remain and will likely delay any practical implementation of EUV lithography for several years. In addition to the problems and limitations of the fabrication processes described above with regard to the fabrication of vias and contacts, it will further be appreciated that similar challenges exist with regard to the fabrication of the integrated circuits within the layers.
Block copolymer (BCP) patterning has attracted attention as a possible solution to the problem of creating patterns with smaller dimensions. Under the right conditions, the blocks of such copolymers phase separate into microdomains (also known as “microphase-separated domains” or “domains”) to reduce the total free energy, and in the process, nanoscale features of dissimilar chemical composition are formed. The ability of block copolymers to form such features recommends their use in nanopatterning, and to the extent that features with smaller CDs can be formed, this should enable the construction of features which would otherwise be difficult to print using conventional lithography. However, without any guidance from the substrate, the microdomains in a self-assembled block copolymer thin film are typically not spatially registered or aligned.
To address the problem of spatial registration and alignment, directed self-assembly (DSA) has been used. This is a method that combines aspects of self-assembly with a lithographically defined substrate to control the spatial arrangement of certain self-assembled BCP domains. One DSA technique is graphoepitaxy, in which self-assembly is guided by topographical features of lithographically pre-patterned substrates. BCP graphoepitaxy provides sub-lithographic, self-assembled features having a smaller characteristic dimension than that of the prepattern itself. DSA is currently thought to be applicable to fabrication of both interconnects (e.g. using graphoepitaxy direction) and the integrated circuits within layers (e.g. using chemoepitaxy).
Embodiments of the present disclosure are directed to methods for directed self-assembly process/proximity correction (DSA PC) in the design of integrated circuits (IC). The purpose of directed self-assembly process/proximity correction in the design of integrated circuits is to predict the shapes of the DSA directing patterns (for example, shapes of the confinement wells in graphoepitaxy or the chemoepitaxy pre-patterns) resulting in desired DSA patterns on a silicon wafer used to produce the integrated circuit. DSA PC is also referred to in the art as a solution of an inverse DSA problem.
Various methods for DSA PC are known in the art. In one example, H.-S. Philip Wong et al. disclose an experimental method to solve a DSA PC problem for a particular case of contact holes patterned using DSA graphoepitaxy. (See “Block Copolymer Directed Self-Assembly Enables Sublithographic Patterning for Device Fabrication”, an oral presentation at the SPIE Advanced Lithography 2012 Symposium, to be published in the SPIE Advanced Lithography 2012 conference proceedings). This method requires creation of “an alphabet”—a set of small contact hole arrays, where each array is patterned using a confinement well of a particular shape. The shape of each confinement well is designed by performing parametric studies experimentally. For each contact hole array from this alphabet, such study requires patterning parameterized families of confinement wells, performing DSA in each of these wells, measuring the results of these DSA processes and determining the ranges of the parameters resulting in the desired placement of the contact holes.
However, this prior art method limits the IC design to a limited set of pre-calibrated contact hole arrays, and only in the context of graphoepitaxy. Further, this method requires the performance a large set of experimental measurements. The experimental parameterization/calibration needed for this solution can only be done for a relatively small set of parameters, and can only be varied within limited ranges.
In another example, Chi-Chun Liu et al. disclose a computational method to solve a DSA PC problem for graphoepitaxy. (See “Progress towards the integration of optical proximity correction and directed self-assembly of block copolymers with graphoepitaxy”, SPIE Advanced Lithography 2012 Symposium conference proceedings). In this method, a complex, iterative procedure is required to solve the problem. Further, the method must be coupled with optical proximity correction (OPC) techniques, resulting in a higher computational cost. Just like the prior art example disclosed above, however, this example is limited to contact hole arrays, and only in the context of graphoepitaxy. Further, this method has a higher computational cost, due to the iterative nature of the method.
As such, what is needed in the art is a simple, cost effective method for directed self-assembly process/proximity correction that overcomes the problems encountered in prior art methods. Furthermore, other desirable features and characteristics of the inventive subject matter will become apparent from the subsequent detailed description of the inventive subject matter and the appended claims, taken in conjunction with the accompanying drawings and this background of the inventive subject matter.